Folgender Benutzer sagt Danke zu bataais für den nützlichen Beitrag: | ||
Mike (07.05.2020) |
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Re: Novag Delta-1 code
Nothing strange there:
Delta-1 2332 ROM _CE1 = A13 CE 2 = RD |
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AW: Novag Delta-1 code
Hi,
I let Arena play two games (15s/move) between both versions. As black, Bataais' hacked version cleaned up material, reaching an overwhelming king + 2 rooks, 1 bishop, 2 knights and 4 pawn against genuine Delta-1's isolated king - but the game ended in a draw (3-fold rep). As white, the hacked version won by checkmate with a large material advantage (king + 1 queen, 1 rook, 1 bishop, 1 knight, 4 pawns against king + 1 rook, 1 bishop, 1 pawn). How to play both: surely many ways, this one is quite simple - in MessChess, I created a hacked_roms new directory containing Bataais' ROM - in Arena, I duplicated my Delta-1 engine and updated each with command line parameters: ccdelta1 -rompath romsYou need to specify both, as without -rompath parameter the default is used from ccdelta1.ini file, where the latest used configuration is memorized. So better force it, or you will end using the hacked one anyway. Of course, on hacked engine start, you need to manually skip the warning about the unexpected ROM. Have fun, Eric |
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Re: Novag Delta-1 code
Congratulations on the work unravelling the Delta-1 puzzle.
It seems like a further chess programming scandal has been revealed this time 40 years after the event. When Data Cash Systems lost their court case and appeal it looks like Novag/SciSys took another liberty and pirated a second chess program for use in one of their models. This time Boris for the Delta-1. I have updated my webpage on the Delta-1. http://www.chesscomputeruk.com/html/...n_delta-1.html Pirate regards Mike |
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AW: Novag Delta-1 code
Thanks, Mike!
I finally managed to get the eprom working in my Delta-1! Only had to invert the CE2 signal. Luckily there was a NOR 4001 already present which inverted it for the RAM 2111 chips. (Chip Selects are always confusing when replacing mask-roms with eproms..) Sorry if I rushed into wrong conclusions about MAME, really nothing wrong there, except I was bewildered by the different moves compared to the real Delta-1. (I haven't played much on the original, since I got it only yesterday ) I believe the uninitialized (randomized) RAM in MAME lets it play other moves. Some pictures for those who want to replicate my hack. Be careful with the screws, I broke the plastic holders. Now I will play some games.. EDIT: After playing some games, there's still something wrong, pieces get lost or appear in RAM.. Ich muss nochmals über die Bücher Geändert von bataais (08.05.2020 um 10:33 Uhr) Grund: Beta-Version |
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Re: Novag Delta-1 code
Right, MAME fills the RAM with rand() which will be different to a real Delta-1. I don't think an SRAM chip will be 100% random at power-on, it will have a pattern. Maybe some of the bits are truly 'random' (with parameters: temperature, magnetic field, slight voltage differences, ...)
This addressing thing won't work on the real chesscomputer, it will put the ROM table before RAM: remove: map(0x2000, 0x20ff).mirror(0x1f00).ram(); // A13 add: map(0x2bc0, 0x2bff).rom().region("maincpu", 0x0880); map(0x2c00, 0x2cff).ram(); |
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AW: Novag Delta-1 code
hap, I thought this adressing scheme should work on the real machine.
RAM gets adressed from EC00 to ECFF (in fact only bit 13 toggles RAM or ROM access, and RAM uses only 8 bits). So if I place the 64-bytes table in RAM at 20C0 or EBC0 or ECC0 should result in the same thing. Now if the DCO (Data counter) accesses the RAM at EC00, then decrements to EBFF, that should still access RAM at 2xFF or EBFF.. (The table HAS to be before RAM start, on the wrap-around.) Am I wrong somewhere? |
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Re: Novag Delta-1 code
What the code above does, it places a part of the ROM at ebc0-ebff, so the reads from uninitialized RAM are now from the table at 0x5880.
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Re: Novag Delta-1 code
Did you get good at F8 asm?
You know, it is possible to make a testrom for finding out the initial SRAM contents to see if there is a specific pattern that can be imitated on MAME. Delta-1 has 4 digits. You could read from RAM and show it on the display(2 digits for address, 2 for data) with half a second delay after each read, do this in a loop 256 times. |
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AW: Novag Delta-1 code
Funny idea!
I didn't do much F8-assembly besides the copy table routine, but learned some when on-the-fly disassembling Boris / Delta-1. I worked more on the soldering side. Tried all possible Chip Select combinations for the EPROM, but the strange RAM behavior still happens. These are the two most logical connections, they work for a while, but then pieces get lost or appear in RAM (Version 2), the display begins to flicker and gets garbled (Version 1). I also tried tying one of the CE's to GND. I believe my EPROM's aren't either fast enough or that /OE (Vpp) pin isn't TTL compatible. Code:
Original Mask-ROM Version (A-11 of 2332 Mask-ROM is pin 18!) F8-3853 A13 ------------> /CE1 of 2332 Mask ROM (pin 20) (pin 30) | | |\ ---| |o----> /CE1 of 2111 RAM (pin 15) |/ CPU READ ------------> CE2 of 2332 Mask ROM (pin 21) (pin 34) | | |\ ---| |o----> Out Disable of 2111 RAM (pin 9) |/ Eprom-Version 1 (A-11 of 2732 Eprom is pin 21!) F8-3853 A13 ------------> /E of 2732 Eprom (pin 18) (pin 30) | | |\ |--| |o----> /CE1 of 2111 RAM (pin 15) |/ |-> /OE (Vpp) of 2732 Eprom (pin 20) | CPU |\ | READ ---| |o----> Out Disable of 2111 RAM (pin 9) (pin 34) |/ Eprom-Version 2 F8-3853 A13 ------------> /OE (Vpp) of 2732 Eprom (pin 20) (pin 30) | | |\ |--| |o----> /CE1 of 2111 RAM (pin 15) |/ |-> /E of 2732 Eprom (pin 18) | CPU |\ | READ ----| |o----> Out Disable of 2111 RAM (pin 9) (pin 34) |/ |
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